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[PATCH] Shut up warnings in sparc.c
- To: "David S. Miller" <davem at redhat dot com>, Richard Henderson <rth at cygnus dot com>
- Subject: [PATCH] Shut up warnings in sparc.c
- From: Jakub Jelinek <jakub at redhat dot com>
- Date: Fri, 24 Mar 2000 14:47:59 +0100
- Cc: gcc-patches at gcc dot gnu dot org
Hi!
This patch kills all warnings in sparc.c (without it I get zillions of
warning: integer constant is unsigned in ANSI C, signed with -traditional
warnings).
Ok to install?
2000-03-24 Jakub Jelinek <jakub@redhat.com>
* config/sparc/sparc.c (arith_operand): Shut up warnings
by adding U suffix to hexadecimal constants.
(arith_4096_operand, const64_operand, const64_high_operand,
uns_small_int, input_operand, sparc_emit_set_const32,
GEN_HIGHINT64, GEN_INT64, sparc_emit_set_const64_quick1,
sparc_emit_set_const64_quick2, sparc_emit_set_const64_longway,
const64_is_2insns, sparc_emit_set_const64, print_operand,
output_double_int, sparc_initialize_trampoline,
sparc64_initialize_trampoline, set_extends): Likewise.
* config/sparc/sparc.h (SMALL_INT32, SPARC_SETHI_P): Likewise.
--- gcc/config/sparc/sparc.c.jj Fri Mar 24 09:17:11 2000
+++ gcc/config/sparc/sparc.c Fri Mar 24 14:25:24 2000
@@ -891,7 +891,7 @@ arith_operand (op, mode)
return 1;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
+ val = INTVAL (op) & 0xffffffffU;
return SPARC_SIMM13_P (val);
}
@@ -905,7 +905,7 @@ arith_4096_operand (op, mode)
int val;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
+ val = INTVAL (op) & 0xffffffffU;
return val == 4096;
}
@@ -933,8 +933,8 @@ const64_operand (op, mode)
|| (GET_CODE (op) == CONST_DOUBLE
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
&& (CONST_DOUBLE_HIGH (op) ==
- ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
- (HOST_WIDE_INT)0xffffffff : 0)))
+ ((CONST_DOUBLE_LOW (op) & 0x80000000U) != 0 ?
+ (HOST_WIDE_INT)0xffffffffU : 0)))
#endif
);
}
@@ -946,7 +946,7 @@ const64_high_operand (op, mode)
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return ((GET_CODE (op) == CONST_INT
- && (INTVAL (op) & 0xfffffc00) != 0
+ && (INTVAL (op) & 0xfffffc00U) != 0
&& SPARC_SETHI_P (INTVAL (op))
#if HOST_BITS_PER_WIDE_INT != 64
/* Must be positive on non-64bit host else the
@@ -957,7 +957,7 @@ const64_high_operand (op, mode)
)
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
- && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
+ && (CONST_DOUBLE_LOW (op) & 0xfffffc00U) != 0
&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
}
@@ -1120,13 +1120,13 @@ uns_small_int (op, mode)
/* All allowed constants will fit a CONST_INT. */
return (GET_CODE (op) == CONST_INT
&& ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
- || (INTVAL (op) >= 0xFFFFF000
+ || (INTVAL (op) >= 0xFFFFF000U
&& INTVAL (op) < 0x100000000)));
#else
return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
- && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
+ && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000U < 0x1000));
#endif
}
@@ -1185,7 +1185,7 @@ input_operand (op, mode)
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
#else
(SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
- && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
+ && (((CONST_DOUBLE_LOW (op) & 0x80000000U) == 0
&& CONST_DOUBLE_HIGH (op) == 0)
|| (CONST_DOUBLE_HIGH (op) == -1)))
#endif
@@ -1267,18 +1267,18 @@ sparc_emit_set_const32 (op0, op1)
values if it wants. */
if (TARGET_ARCH64
&& HOST_BITS_PER_WIDE_INT != 64
- && (INTVAL (op1) & 0x80000000) != 0)
+ && (INTVAL (op1) & 0x80000000U) != 0)
{
emit_insn (gen_rtx_SET (VOIDmode,
temp,
gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
- INTVAL (op1) & 0xfffffc00, 0)));
+ INTVAL (op1) & 0xfffffc00U, 0)));
}
else
{
emit_insn (gen_rtx_SET (VOIDmode,
temp,
- GEN_INT (INTVAL (op1) & 0xfffffc00)));
+ GEN_INT (INTVAL (op1) & 0xfffffc00U)));
}
emit_insn (gen_rtx_SET (VOIDmode,
op0,
@@ -1438,17 +1438,17 @@ static rtx gen_safe_OR64 PARAMS ((rtx, H
static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
#if HOST_BITS_PER_WIDE_INT == 64
-#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
+#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00U)
#define GEN_INT64(__x) GEN_INT (__x)
#else
#define GEN_HIGHINT64(__x) \
gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
- (__x) & 0xfffffc00, 0)
+ (__x) & 0xfffffc00U, 0)
#define GEN_INT64(__x) \
gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
- (__x) & 0xffffffff, \
- ((__x) & 0x80000000 \
- ? 0xffffffff : 0))
+ (__x) & 0xffffffffU, \
+ ((__x) & 0x80000000U \
+ ? 0xffffffffU : 0))
#endif
/* The optimizer is not to assume anything about exactly
@@ -1509,7 +1509,7 @@ sparc_emit_set_const64_quick1 (op0, temp
unsigned HOST_WIDE_INT high_bits;
if (is_neg)
- high_bits = (~low_bits) & 0xffffffff;
+ high_bits = (~low_bits) & 0xffffffffU;
else
high_bits = low_bits;
@@ -1552,10 +1552,10 @@ sparc_emit_set_const64_quick2 (op0, temp
{
rtx temp2 = op0;
- if ((high_bits & 0xfffffc00) != 0)
+ if ((high_bits & 0xfffffc00U) != 0)
{
sparc_emit_set_safe_HIGH64 (temp, high_bits);
- if ((high_bits & ~0xfffffc00) != 0)
+ if ((high_bits & ~0xfffffc00U) != 0)
emit_insn (gen_rtx_SET (VOIDmode, op0,
gen_safe_OR64 (temp, (high_bits & 0x3ff))));
else
@@ -1598,10 +1598,10 @@ sparc_emit_set_const64_longway (op0, tem
else
sub_temp = gen_reg_rtx (DImode);
- if ((high_bits & 0xfffffc00) != 0)
+ if ((high_bits & 0xfffffc00U) != 0)
{
sparc_emit_set_safe_HIGH64 (temp, high_bits);
- if ((high_bits & ~0xfffffc00) != 0)
+ if ((high_bits & ~0xfffffc00U) != 0)
emit_insn (gen_rtx_SET (VOIDmode,
sub_temp,
gen_safe_OR64 (temp, (high_bits & 0x3ff))));
@@ -1625,7 +1625,7 @@ sparc_emit_set_const64_longway (op0, tem
GEN_INT (32))));
sparc_emit_set_safe_HIGH64 (temp2, low_bits);
- if ((low_bits & ~0xfffffc00) != 0)
+ if ((low_bits & ~0xfffffc00U) != 0)
{
emit_insn (gen_rtx_SET (VOIDmode, temp3,
gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
@@ -1766,7 +1766,7 @@ const64_is_2insns (high_bits, low_bits)
int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
if (high_bits == 0
- || high_bits == 0xffffffff)
+ || high_bits == 0xffffffffU)
return 1;
analyze_64bit_constant (high_bits, low_bits,
@@ -1846,8 +1846,8 @@ sparc_emit_set_const64 (op0, op1)
if (GET_CODE (op1) == CONST_DOUBLE)
{
#if HOST_BITS_PER_WIDE_INT == 64
- high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
- low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
+ high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffffU;
+ low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffffU;
#else
high_bits = CONST_DOUBLE_HIGH (op1);
low_bits = CONST_DOUBLE_LOW (op1);
@@ -1856,11 +1856,11 @@ sparc_emit_set_const64 (op0, op1)
else
{
#if HOST_BITS_PER_WIDE_INT == 64
- high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
- low_bits = (INTVAL (op1) & 0xffffffff);
+ high_bits = ((INTVAL (op1) >> 32) & 0xffffffffU);
+ low_bits = (INTVAL (op1) & 0xffffffffU);
#else
high_bits = ((INTVAL (op1) < 0) ?
- 0xffffffff :
+ 0xffffffffU :
0x00000000);
low_bits = INTVAL (op1);
#endif
@@ -1963,10 +1963,10 @@ sparc_emit_set_const64 (op0, op1)
* xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
*/
if (high_bits == 0
- || high_bits == 0xffffffff)
+ || high_bits == 0xffffffffU)
{
sparc_emit_set_const64_quick1 (op0, temp, low_bits,
- (high_bits == 0xffffffff));
+ (high_bits == 0xffffffffU));
return;
}
@@ -1984,22 +1984,22 @@ sparc_emit_set_const64 (op0, op1)
/* We may be able to do something quick
when the constant is negated, so try that. */
- if (const64_is_2insns ((~high_bits) & 0xffffffff,
- (~low_bits) & 0xfffffc00))
+ if (const64_is_2insns ((~high_bits) & 0xffffffffU,
+ (~low_bits) & 0xfffffc00U))
{
/* NOTE: The trailing bits get XOR'd so we need the
non-negated bits, not the negated ones. */
unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
- if ((((~high_bits) & 0xffffffff) == 0
- && ((~low_bits) & 0x80000000) == 0)
- || (((~high_bits) & 0xffffffff) == 0xffffffff
- && ((~low_bits) & 0x80000000) != 0))
+ if ((((~high_bits) & 0xffffffffU) == 0
+ && ((~low_bits) & 0x80000000U) == 0)
+ || (((~high_bits) & 0xffffffffU) == 0xffffffffU
+ && ((~low_bits) & 0x80000000U) != 0))
{
- int fast_int = (~low_bits & 0xffffffff);
+ int fast_int = (~low_bits & 0xffffffffU);
if ((SPARC_SETHI_P (fast_int)
- && (~high_bits & 0xffffffff) == 0)
+ && (~high_bits & 0xffffffffU) == 0)
|| SPARC_SIMM13_P (fast_int))
emit_insn (gen_safe_SET64 (temp, fast_int));
else
@@ -2009,12 +2009,12 @@ sparc_emit_set_const64 (op0, op1)
{
rtx negated_const;
#if HOST_BITS_PER_WIDE_INT == 64
- negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
- (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
+ negated_const = GEN_INT (((~low_bits) & 0xfffffc00U) |
+ (((HOST_WIDE_INT)((~high_bits) & 0xffffffffU))<<32));
#else
negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
- (~low_bits) & 0xfffffc00,
- (~high_bits) & 0xffffffff);
+ (~low_bits) & 0xfffffc00U,
+ (~high_bits) & 0xffffffffU);
#endif
sparc_emit_set_const64 (temp, negated_const);
}
@@ -5813,7 +5813,7 @@ print_operand (file, x, code)
/* Print a sign-extended character. */
int i = INTVAL (x) & 0xff;
if (i & 0x80)
- i |= 0xffffff00;
+ i |= 0xffffff00U;
fprintf (file, "%d", i);
return;
}
@@ -5898,8 +5898,8 @@ output_double_int (file, value)
HOST_WIDE_INT xword = INTVAL (value);
HOST_WIDE_INT high, low;
- high = (xword >> 32) & 0xffffffff;
- low = xword & 0xffffffff;
+ high = (xword >> 32) & 0xffffffffU;
+ low = xword & 0xffffffffU;
ASM_OUTPUT_INT (file, GEN_INT (high));
ASM_OUTPUT_INT (file, GEN_INT (low));
#else
@@ -6136,13 +6136,13 @@ sparc_initialize_trampoline (tramp, fnad
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
expand_binop (SImode, ior_optab,
expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
- GEN_INT (0x81c06000),
+ GEN_INT (0x81c06000U),
NULL_RTX, 1, OPTAB_DIRECT));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
expand_binop (SImode, ior_optab,
expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
- GEN_INT (0x8410a000),
+ GEN_INT (0x8410a000U),
NULL_RTX, 1, OPTAB_DIRECT));
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
@@ -6175,13 +6175,13 @@ sparc64_initialize_trampoline (tramp, fn
*/
emit_move_insn (gen_rtx_MEM (SImode, tramp),
- GEN_INT (0x83414000));
+ GEN_INT (0x83414000U));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
- GEN_INT (0xca586018));
+ GEN_INT (0xca586018U));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
- GEN_INT (0x81c14000));
+ GEN_INT (0x81c14000U));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
- GEN_INT (0xca586010));
+ GEN_INT (0xca586010U));
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
@@ -7990,9 +7990,9 @@ set_extends(x, insn)
return GET_MODE (SET_SRC (pat)) == SImode;
/* Positive integers leave the high bits zero. */
case CONST_DOUBLE:
- return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
+ return ! (CONST_DOUBLE_LOW (x) & 0x80000000U);
case CONST_INT:
- return ! (INTVAL (x) & 0x80000000);
+ return ! (INTVAL (x) & 0x80000000U);
case ASHIFTRT:
case SIGN_EXTEND:
return - (GET_MODE (SET_SRC (pat)) == SImode);
--- gcc/config/sparc/sparc.h.jj Fri Mar 24 09:17:10 2000
+++ gcc/config/sparc/sparc.h Fri Mar 24 14:13:09 2000
@@ -1426,10 +1426,10 @@ extern char leaf_reg_remap[];
SMALL_INT is used throughout the port so we continue to use it. */
#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
+#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffffU))
#define SPARC_SETHI_P(X) \
(((unsigned HOST_WIDE_INT) (X) & \
- (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
+ (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00U : 0x3ff)) == 0)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
Cheers,
Jakub
___________________________________________________________________
Jakub Jelinek | jakub@redhat.com | http://sunsite.mff.cuni.cz/~jj
Linux version 2.3.99-pre2 on a sparc64 machine (1343.49 BogoMips)
___________________________________________________________________