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[patch] h8300.md: Add extendqisi2 for H8/300H and H8S.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 19 Feb 2003 08:00:37 -0500 (EST)
- Subject: [patch] h8300.md: Add extendqisi2 for H8/300H and H8S.
Hi,
Attached is a patch to add extendqisi2 for H8/300H and H8S.
When the combiner creates (sign_extend:SI (mem:QI ...)), the pattern
gets split into two 24-bit shifts, one ashift and one ashiftrt. This
is quite inefficient. The patch prevents this by adding extend_qisi2
pattern for H8/300H and H8S and splitting that later.
In terms of assembly code,
mov.b r0l,r0h ; the beginning of << 24
sub.b r0l,r0l
mov.w r0,e0
sub.w r0,r0
mov.w e0,r0 ; the beginning of >> 24
mov.b r0h,r0l
exts.w r0
exts.l er0
becomes
exts.w r0
exts.l er0
Tested on h8300 port. Committed.
Kazu Hirata
2003-02-19 Kazu Hirata <kazu at cs dot umass dot edu>
* config/h8300/h8300.md (extendqisi2): Change to an expander.
(*extendqisi2_h8300): New.
(*extendqisi2_h8300hs): Likewise.
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.169
diff -u -r1.169 h8300.md
--- h8300.md 19 Feb 2003 12:53:32 -0000 1.169
+++ h8300.md 19 Feb 2003 12:59:07 -0000
@@ -2101,10 +2101,14 @@
[(set_attr "length" "2")
(set_attr "cc" "set_znv")])
-;; The compiler can synthesize a H8/300H variant of this which is
-;; just as efficient as one that we'd create
-(define_insn "extendqisi2"
+(define_expand "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
+ (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
+ ""
+ "")
+
+(define_insn "*extendqisi2_h8300"
+ [(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
"TARGET_H8300"
"@
@@ -2112,6 +2116,22 @@
mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
[(set_attr "length" "8,12")
(set_attr "cc" "clobber,clobber")])
+
+;; The following pattern is needed because without the pattern, the
+;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
+;; shifts, one ashift and one ashiftrt.
+
+(define_insn_and_split "*extendqisi2_h8300hs"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (sign_extend:HI (match_dup 1)))
+ (set (match_dup 0)
+ (sign_extend:SI (match_dup 2)))]
+ "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
(define_expand "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "")